The present invention relates generally to semiconductor integrated circuits and more particularly to a semiconductor integrated circuit having a plurality of inputs such as a decoder circuit of a semiconductor memory.
In order to reduce the size of a semiconductor device, such as a dynamic random access memory (DRAM), component density has continued to increase. As the circuit and wiring miniaturization has increased, the demand for lower power consumption has increased. One method of decreasing power consumption has been to decrease the internal power supply voltage used by the on-chip circuitry.
In general, when the power supply voltage is decreased, gate delay time (tpd) increases which decreases the device operation speed. In order to minimize the gate delay time, the threshold voltage of transistors such as metal oxide semiconductor field effect transistors (MOSFET) can be decreased. This can have the affect of increasing transconductance (gm) so the drive strength can be improved. However, when the threshold voltage is made small, sub-threshold current increases which can cause an increase in standby current and power consumption.
An approach directed to improve the sub-threshold current problem has been disclosed in Japanese Patent Laid-Open No. 6-208790 (JP 6-208790) and will be explained with reference to FIG. 9. Referring now to FIG. 9, a circuit schematic diagram illustrating a conventional string of inverters is set forth. Each inverter is configured as a CMOS (complementary metal oxide semiconductor) inverter in which there is a n-type MOSFET and a p-type MOSFET. For example, the initial stage inverter is made up of n-type MOSFET Q1 and p-type MOSFET Q3. The subsequent stage inverter is made up of n-type MOSFET Q2 and p-type MOSFET Q4.
In the string of inverters illustrate in FIG. 9, the threshold voltage of the transistors that are to be turned off during standby have been increased and are larger than the threshold voltage of the transistors that are turned on in standby. In this example, when the semiconductor device is in standby, a logic low is input into the initial stage inverter (Q1 and Q3). In this state, n-type MOSFET Q1 and p-type MOSFET Q4 are turned off. Accordingly, n-type MOSFET Q1 has a threshold voltage VT1 that is set higher than the threshold voltage VT2 of n-type MOSFET Q2. Likewise, p-type MOSFET Q4 has a threshold voltage VT4 that is higher than the threshold voltage VT3 of p-type MOSFET Q3.
In this way, when the input signal of the initial stage inverter (Q1 and Q3) is low, the string of inverters is in the standby state. In this standby state, n-type MOSFET Q1 and p-type MOSFET Q4 are turned off while n-type MOSFET Q2 and p-type MOSFET Q3 are turned on. With p-type transistor Q3 turned on, a low impedance path is created through p-type transistor Q3 to the power supply. However, because n-type MOSFET Q1 has a high threshold voltage VT1, the sub-threshold leakage current is reduced. Thus, the current leaking from the power supply to ground is reduced in the standby state. Because the output of the initial stage inverter (Q1 and Q3) is logic high, n-type MOSFET Q2 is turned on and p-type MOSFET Q4 is turned off. With n-type transistor Q2 turned on, a low impedance path is created through n-type transistor Q2 to the ground potential. However, because p-type MOSFET Q4 has a high threshold voltage VT4, the sub-threshold leakage current is reduced. Thus, the current leaking from the power supply to ground is reduced in the standby state.
However, the approach described in JP 6-208790 can have drawbacks. For example, in the case of a circuit system in which one logic gate drives a plurality of logic gates the gate delay time (tpd) and the stand-by current may not be effectively improved. One such example can be illustrated by considering a decoder of a semiconductor memory.
First, reasons why the gate delay time (tpd) may not be improved will be described.
Referring now to FIG. 10(a), a circuit schematic diagram of a conventional decoder used in a semiconductor memory device is set forth.
The decoder of FIG. 10(a) uses the approach set forth in JP 6-208790. In this case, when the decoder is in the standby state, transistors that are turned off have a high threshold voltage. As illustrated in FIG. 10, inverter 510 is a driver circuit used to drive a block selection line 520. Inverter 530 is a driver circuit used to drive main word line 540. Block selection line 520 and main word line 540 are used to select logic circuit 550. Logic circuit 550 is used to drive a sub-word line. There are a plurality of block selection lines 520 and main word lines 540 disposed perpendicular to each other. A logic circuit 550 is disposed at intersecting points of a main word line 540 and block selection line 520.
Block selection line 520 is connected to a plurality of logic circuits 550 in the column direction. Thus, inverter 510 is configured to drive the plurality of logic circuits 550. Additionally, main word line 540 is connected to a plurality of logic circuits 550 in the row direction. Likewise, inverter 530 is configured to drive the plurality of logic circuits 550.
Inverters (510 and 530) each drive a plurality of logic circuits 550, however, only the logic circuit 550 that receives a high logic level from block selection line 520 and main word line 540 is selected. Logic circuits 550 that receive a low logic level from either block selection line 520 or main word line 540 are in a non-selection state.
Logic circuit 550 consists of a NAND gate 551 and an inverter 552 that are together configured to produce a logical AND output of the signals received on the block selection line 520 and main word line 540. NAND gate 551 receives block selection line 520 and main word line 540 and produces an output that is received as an input of inverter 552. Inverter 552 produces an output that is a sub-word line signal.
Referring now to FIG. 10(b), a circuit schematic diagram of NAND 551 is set forth. NAND 551 is a CMOS NAND gate that has p-type MOSFETs (5511 and 5512) and n-type MOSFETs (5513 and 5514). P-type MOSFET 5511 has a source connected to a power supply, a drain connected to an output, and a gate connected to block selection line 520. P-type MOSFET 5512 has a source connected to a power supply, a drain connected to an output, and a gate connected to main word line 540. N-type MOSFET 5513 has a source connected to a drain of n-type MOSFET 5514, a drain connected to the output and a gate connected to block selection line 5513. N-type MOSFET 5514 has a source connected to ground and a gate connected to main word line 540.
In the conventional decoder as illustrated in FIG. 10, p-type MOSFET 5511 and n-type MOSFET 5513 will be switched in a complementary fashion in accordance with the signal level on block selection line 520. Likewise, p-type MOSFET 5512 and n-type MOSFET 5514 will be switched in a complementary fashion in accordance with the signal level on main word line 540.
The gate capacitance of a MOSFET is significantly larger when the MOSFET is turned on than when it is turned off. Block selection line 520 is connected to a plurality of logic circuits 550. Because block selection line 520 is connected to a p-type MOSFET 5511 and a n-type MOSFET 5513, there is always a MOSFET that is turned on. When block selection line 520 is low, p-type MOSFET 5511 is turned on and has increased capacitance. When block selection line 520 is high, n-type MOSFET 5513 is turned on and has increased capacitance. Thus, the capacitive load on block selection line 520 is always relatively large. This can increase the gate delay time of inverter 520 and can affect the overall circuit operating speed.
Additionally, when the threshold voltage of a MOSFET is decreased to compensate for a decreased power supply potential, the particular MOSFET turns on more quickly when the switching signal transitions thereby increasing the gate capacitance earlier. This can increase the total charge needed to drive the gate of the MOSFET and further decrease the logic gate delay time (tpd). Thus, when using the conventional approach in a circuit such as a decoder, for example, the logic gate delay time (tpd) is not effectively improved when the threshold voltage of a MOSFET is decreased to compensate for a decreased power supply potential.
The reason why the stand-by current may not be improved will now be described.
In the conventional decoder configuration illustrated in FIG. 10, the circuit may be in a stand-by condition when block selection line 520 is low. However, main word line 540 can be high. In this case, n-type MOSFET 5513 is turned off and p-type MOSFET 5511 is turned on. Also, p-type MOSFET 5512 is turned off and n-type MOSFET 5514 is turned on. Thus, a potential difference equivalent to the power supply is applied between the drain and source of n-type MOSFET 5513. This can cause a sub-threshold current to flow from the power supply to ground through n-type MOSFET 5513. In the case of a semiconductor memory, the row decoder includes a plurality of logic circuits 550, thus, even if the threshold voltage of the transistor that is turned off in stand-by is relatively high, it is problematic to effectively improve the stand-by current.
In view of the above discussion, it would be desirable to provide a semiconductor integrated circuit that can effectively improve the gate delay time even if the threshold voltage of a transistor is decreased in conjunction with a decreased in the power supply potential. It would also be desirable to effectively decrease the stand-by current even if the threshold voltage of a transistor is decreased in conjunction with a decreased in the power supply potential. It would also be desirable to provide these improvements in a circuit such as a decoder in a semiconductor memory in which one driver circuit drives a plurality of logic circuits.
According to the present embodiments, a semiconductor integrated circuit may include a logic circuit having a insulated gate field effect transistor (IGFET) with a reduced threshold voltage that may compensate for a reduced voltage supply is provided. The IGFET may receive a signal line at a gate terminal and may provide a controllable impedance path between a signal line and a node. The logic circuit may include a stand-by mode in which the IGFET may receive a potential at a source electrode that may be approximately equal to the potential at a drain electrode. In this way, leakage current may be reduced.
According to one aspect of the embodiments, a semiconductor integrated circuit may include a plurality of logic circuit coupled to receive a first signal line from a first drive circuit. Each logic circuit may include a first conductivity type IGFET having a first threshold voltage, a second first conductivity type IGFET having a second threshold voltage, and an output node. The first threshold voltage may be smaller than the second threshold voltage. The first conductivity type IGFET may have a gate electrode coupled to receive the first signal line and may provide a first controllable impedance path between one of a plurality of second signal lines and the output node.
According to another aspect of the embodiments, each logic circuit may include a load device coupled between a power supply and the output node and provide charge to the output node.
According to another aspect of the embodiments, when the logic circuit is in a non-selected state, the first conductivity type IGFET may have a potential difference between a source electrode and a drain electrode that may be less than the first threshold voltage.
According to another aspect of the embodiments, when the logic circuit is in a non-selected state, the first conductivity type IGFET may have a potential at a source electrode that may be substantially equal to a potential at a drain electrode.
According to another aspect of the embodiments, each logic circuit may include an inverter having an input coupled to receive the output node. The inverter may include a first conductivity type IGFET and a second conductivity type IGFET. The second conductivity type IGFET may have a threshold voltage that may be higher than a typical second conductivity type IGFET.
According to another aspect of the embodiments, each second signal line may be driven to a maximum voltage of approximately the power supply minus the first threshold voltage by one of a plurality of second drive circuits.
According to another aspect of the embodiments, each second signal line may be driven by one of a plurality of second drive circuits. Each second drive circuit may include a first conductivity type IGFET and a second conductivity type IGFET arranged to form an inverter driving the second signal line. The first drive circuit may include a first conductivity type IGFET and a second conductivity type IGFET arranged to form an inverter driving the first signal line. The second conductivity type IGFET in the first drive circuit may have a higher threshold voltage than a typical second conductivity type IGFET on the semiconductor integrated circuit. The first conductivity type IGFET in the second drive circuit may have a higher threshold voltage than a typical first conductivity type IGFET on the semiconductor integrated circuit
According to another aspect of the embodiments, the plurality of logic circuits may be coupled to receive a third signal line from a third drive circuit. Each logic circuit may include a first conductivity type IGFET having a gate electrode coupled to receive the third signal line and providing a second controllable impedance path between the first controllable impedance path and the output node.
According to another aspect of the embodiments, a connection node between the first conductivity type IGFETs may be charged by a charging IGFET, which may prevent a floating condition.
According to another aspect of the embodiments, a semiconductor integrated circuit may include a first signal line disposed perpendicularly to a second signal line. A logic circuit may include a first conductivity type IGFET having a control gate coupled to the first signal line and providing a first controllable impedance path between the second signal line and a charge node. A second conductivity type IGFET may be coupled between a first reference potential and the charge node and may provide charge to the charge node. The first conductivity type IGFET may have a threshold voltage that may be lower than the threshold voltage of a typical first conductivity type IGFET on the semiconductor integrated circuit According to another aspect of the embodiments, in a standby mode of operation, the first signal line may be at a first logic level and the second signal line may be at a second logic level.
According to another aspect of the embodiments, the first logic level may be a low logic level and the second logic level may be a high logic level. The first conductivity type may be n-type.
According to another aspect of the embodiments, a first drive circuit may include a second conductivity type IGFET. The second conductivity type IGFET may have a controllable impedance path coupled between the first reference potential and the first signal line. The second conductivity type IGFET may have a threshold voltage that may be higher than a typical second conductivity type IGFET on the semiconductor integrated circuit. A second drive circuit may include a first conductivity type IGFET. The first conductivity type IGFET may have a controllable impedance path coupled between a second reference potential and the second signal line. The first conductivity type IGFET may have a threshold voltage that may be higher than a typical first conductivity type IGFET on the semiconductor integrated circuit.
According to another aspect of the embodiments, the semiconductor integrated circuit may include a standby mode in which the charge node has essentially the same potential as the second signal line.
According to another aspect of the embodiments, the logic circuit may include a second conductivity type IGFET having a gate coupled to receive the charge node and may provide a controllable impedance path between the first reference potential and a logic circuit output node. The second conductivity type IGFET may have a threshold voltage that may be greater than a typical second conductivity type IGFET on the semiconductor integrated circuit.
According to another aspect of the embodiments, a semiconductor integrated circuit may include a first signal line disposed perpendicularly to a plurality of second signal lines. The semiconductor integrated circuit may include a plurality of logic circuits and a plurality of second signal drive circuits. Each logic circuit may include a first IGFET of a first conductivity type and having a control gate coupled to receive the first signal line and may provide a controllable impedance path between a logic circuit node and one of the plurality of second signal lines. Each second signal drive circuit may include a first second signal drive IGFET of the first conductivity type having a controllable impedance path coupled between a first reference potential and one of the plurality of second signal lines. The first IGFET may have a threshold voltage that is lower than the threshold voltage of the first second signal drive IGFET.
According to another aspect of the embodiments, each second signal drive circuit may be coupled to receive a chip select signal.
According to another aspect of the embodiments, the semiconductor integrated circuit may be a semiconductor memory device including a plurality of sub-word lines. Each logic circuit may have a logic circuit output coupled to one of the plurality of sub-word lines.
According to another aspect of the embodiments, the plurality of logic circuits may be coupled to provide sub-word lines associated with a first sub-array. A third signal line may be disposed perpendicularly to the plurality of second signal lines. The semiconductor integrated circuit may include a second plurality of logic circuits. Each logic circuit may include the first IGFET of a first conductivity type and having a control gate coupled to receive the third signal line and providing a controllable impedance path between the logic circuit node and one of the plurality of second signal lines. The second plurality of logic circuits may be coupled to provide sub-word lines associated with a second sub-array.
According to another aspect of the embodiments, the semiconductor integrated circuit may be an dynamic random access memory and the first and second signal lines may include decoded address information.